As the storage capacity of semiconductor memory devices continues to increase, the number of memory cells included in such memories also increases. With the increase in the number of memory cells, the probability that one or more memory cells are defective is increased. In order to avoid having to discard the memory device due to just one or a few defective memory cells, redundant memory elements are included in the semiconductor memory device. The redundant memory elements are usually rows and/or columns and are used to replace the rows and/or columns that contain defective memory cells.
During wafer testing, all memory cells are tested. The information about which memory cells are defective and sometimes the information about which redundant memory elements are selected to replace the defective memory elements is called redundancy information. After the wafer test the redundancy information is stored in a non-volatile memory in a one-time programming (OTP) operation. During read, write or erase operations, the memory device addresses memory cells. A redundancy control unit accesses the redundancy information to check if the memory cells addressed are functioning or if they need to be replaced by a redundant element. If they are defective, the memory cells will be replaced with redundant elements. As a result, the semiconductor memory device will function as expected and the production yield is significantly increased.
FIG. 1 shows a semiconductor memory device M. The semiconductor memory device M comprises a memory array MA for storing user data, a redundancy array RA providing redundant memory elements, and a non-volatile redundancy information memory NVR for storing redundancy information. The memory cells in the memory array MA and the non-volatile redundancy information memory NVR can be read by means of the sense amplifier SA and written by means of the bitline driver BL while the memory cells in the redundancy array RA can be read by means of the redundancy array sense amplifier RSA and written by means of the redundancy array bitline driver RBL. A bitline multiplexer BLM is used to connect the data bus DB to either the bitline driver BL or to the redundancy array bitline driver RBL, while a sense amplifier multiplexer SAM is used to connect either the sense amplifier SA or the redundancy array sense amplifier RSA to the data bus DB. Both the bitline multiplexer BLM and the sense amplifier multiplexer SAM are controlled by the redundancy control unit RU.
FIG. 1 shows the flow of the redundancy information during power up or during initialization of the semiconductor memory device M. The elements involved are drawn using thicker lines. Memory cells in the non-volatile redundancy information memory NVR are selected by means of the address decoder AD and the redundancy information stored is read by means of the sense amplifier SA. The redundancy control unit RU controls the sense amplifier multiplexer SAM so that the sense amplifier SA is connected to the data bus DB. The redundancy information is then transferred by means of the data bus DB to the redundancy information memory RM. The redundancy information memory RM is usually a static random access memory (SRAM), which allows for fast access of the information stored in it.
FIG. 2 shows the same semiconductor memory device M as in FIG. 1 and illustrates the flow of the redundancy information when memory cells are accessed, such as during read, write, or erase operations. The data path of the redundancy information is again indicated by using thicker lines for the elements involved. Every time a memory cell is accessed, the redundancy information corresponding to the address of the memory cell accessed, is read from the redundancy information memory RM into the redundancy decoder RD, where it is decoded. The redundancy information is then transferred by means of the data bus DB to the redundancy control unit RU. The redundancy control unit RU controls the bitline driver multiplexer BLM and the sense amplifier multiplexer SAM, so that depending on the redundancy information, either a memory cell in the memory array MA or a memory cell in the redundancy array RA is accessed.
The semiconductor memory device M suffers from a number of disadvantages. First, the redundancy information has to be read out of the redundancy information memory RM, decoded by the redundancy decoder RD and then loaded into the redundancy control unit RU every time before a memory cell can be accessed. For these steps, a total number of about twenty clock cycles is necessary, which slows down the access to the memory cells and leads to poor performance. Second, both the redundancy information memory RM and the redundancy decoder RD require chip area. At present, the required chip area amounts to 1.5 mm2.